Basic Information

• Project Title: Review of Clock and Data Recovery circuits for PAM-4 signalling
• Name: Aayush Shrivastava
• Project: SRE
• Semester(s): 2022-23/Autumn
• Guide: Shalabh Gupta

Abstract

Clock and data recovery CMOS circuits for high speed communication protocols like PAM-4 signalling. In higher speed communication it is not possible for sending clock signal along with data so the clock information is extracted from the data and then that clock is used to get the correct data.

Any courses you completed relevant to the project

EE800

Describe your experience on the project

I chose the above guide because I wanted to do a project in analog design and zele refused to take any more projects. I had to review papers for clock and data recovery architectures for PAM-4 signalling. There were 3-4 papers that I reviewed and presented them to the professor. It was just a review of papers so no publication or so. Not working anymore with the professor

Describe your experience with the guide

The work wasn’t much interesting to me barely had any interaction with professor only to the PhD student few times. Sometimes the PhD student cleared doubt but wasn’t very proactive so I lost the interest in the project and just completed for the grade sake. Evaluation wise professor wasn’t happy with the work and presentation he gave a 8. But generally shalab sir gives 9/10 in RnD projects or seminars that’s what his mtech students told me.

Any advice for anyone considering a project under the same guide? Any other professors working in similar fields?

If you interested in communication side of analog Design then he is a good and only prof working on designing serdes and related circuits but in general there are better professors. Laxmeesha sommappa, Rajesh Zele are best for projects in analog design. Maryam’s research is good but she can be a bad guide in terms of logistics as she expects a lot from you.