Basic Information

• Project Title: Logarithmic SAR ADC
• Name: Suraj Sarvesha Samaga
• Project: BTP
• Semester(s): 7, 8
• Guide: Prof. Rajesh Zele

Abstract

Non-linear ADC Design for high dynamic-range applications. The SAR algorithm is modified for logarithmic compatibility and implemented in 65nm CMOS technology.

Any courses you completed relevant to the project

EE 204, EE 618, EE 719

Describe your experience on the project

I wanted to further my interest in Analog Electronics through a concrete project to get some experience under my belt. Prof. Zele is one of the best professors I have learnt under, and I thought that doing a BTP with him would be a tremendous learning experience. I worked in a team of three, and the type of work ranged all the way from concept ideation to circuit implementation and testing on software. The workload was high, especially during the final stages. A Ph.D. student is taking the project forward and will look to publish it soon.

Describe your experience with the guide

My guide was very involved and conducted regular meetings during the ideation phase. After that, the meetings were more on an as-need basis. Prof. Zele was extremely busy, but always took out time for project doubts/discussions and would always encourage open dialogue. The final output was expected to be of a certain quality. The evaluation was fair.

Any advice for anyone considering a project under the same guide? Any other professors working in similar fields?

Effectively manage your schedule so as to allocate enough time for BTP. Try not to treat it like a course project and leave too much for the last minute.