Course: System design (EE668)
Semester: Spring 2017-18
Course Instructor: Prof. Dinesh Sharma and Prof. Shalabh Gupta
Pre-requisites: No pre-requisites are needed to opt for the course. However, concepts of VLSI design are helpful.
Motivation: The course introduces the nitty-gritties involved in designing various practical digital systems. Concepts like high speed data transmission and data security are introduced.
Course Content:
- Transmission lines
- Pipeline optimisation
- PLLs and DLLs
- Equalisers
- Current mode data transmission
- Basic queuing theory
- Various techniques of data encryption
Feedback on Lectures:
A large variety of topics is discussed during the lectures which are quite disparate. Therefore it is difficult to find the material in a book. Attending lectures is helpful in understanding the mindset with which a digital system is designed and the various issues that need to be considered in the process like data transmission, security, integrity, etc. Additionally, a tutorial was conducted for familiarisation with VerilogA.
Feedback on Evaluation:
- 2 Quizzes
- 2 HW Assignments
- Midsem
- Endsem
The 2 homework assignments were both given out after midsems. They had design problems to be done using Cadence’s Virtuoso and VerilogA. Midsem and Endsem questions are based on understanding of notes given by the Professor.
Reviewed by:
Devesh Khilwani (devesh.khilwani@gmail.com)