Basic Information

  • Course Code: EE 671
  • Course Name: VLSI Design
  • Course Offered In: 2023-‘24
  • Semester Season: Autumn
  • Instructors: Prof. Dinesh K Sharma
  • Prerequisites: Familiarity with hardware description languages such as VHDL and circuit simulations using Ngspice is expected. Apart from that exposure to device physics and MOS fundamentals will be beneficial, though the instructor covers these concepts in depth in the first few lectures.
  • Difficulty (1 being easy and 5 being tough): 3

Course Content

  • Semiconductor Basics
  • CMOS Logic Design: Inverter’s Static and Dynamic Characteristics, Noise Margins
  • Other Design Styles: Pseudo nMOS, Dual Rail Logic, Dynamic Logic, Domino and Zipper Logic
  • Synchronous Design: Setup and Hold Time analysis
  • Multi-Stage Logic: the Logical Effort paper, Optimisation of path length and Fork Design
  • Semi-Custom Design: PLAs, Sea of Gates Design, FPGAs
  • Arithmetic Circuits: Optimising Adders, Shifters, Rotaters, Multipliers
  • Memory: SRAM Design, DRAM, Address Decoding in Memories
  • Pipeline Optimisation
  • I/O Circuits: Input Buffers with Hysteresis, Bi-Directional Circuits
  • Asynchronous Design: Static C Element and designing a two-phase Pipeline

Feedback on Lectures

The lectures are thoroughly engaging and the instructor covers concepts in detail. The content of the course is quite big; hence it is beneficial to regularly attend the lectures. The instructor used digital slides as well as the blackboard for explaining concepts. Students were given digital notes as well, which covered everything in detail about what was taught in class. Apart from this, various research papers on which the lecture content was based on were also uploaded for additional reading, which helped in a deeper understanding. The material given by the instructor was more than sufficient. There is no strict policy regarding attendance in lectures.

Feedback on Evaluations

The evaluation policy was as follows

  • 2 Quizzes: 10% each
  • MidSem: 25%
  • EndSem: 40%
  • 4 Assignments: Totalling to 15%

We were allowed multiple cheat sheets for all the exams, so the exams were mostly based on concepts and application of it. Some exams were time-consuming, while others were straightforward. The instructor uploaded problems he had designed for the previous iterations of the course as well, which helped in the practice of the concepts. The evaluation was moderate, and the final grading was decent as well. The first two assignments were based on the sizing of transistors as well as dynamic analysis using Ngspice, while the other two assignments were based on VHDL to design a Brent-Kung Adder and a Dadda Multiplier. The second two assignments were pretty big but were helpful in understanding the niches of the design. Each assignment had a Viva as well.

Study Material and Resources

The material given by the instructor is more than enough.

Follow-up Courses

EE705 (VLSI Design Lab)

Final Takeaway

This course is a kickstart in the area of VLSI Designing. The course was very well taught and executed and should be a sure-shot consideration for whoever wishes to take up Digital Design and Memory Design in the future.