EE 705 – VLSI Design Lab

Course offered in:

Spring 2013-2014

Instructor:

Prof. Virendra Singh

Motivation:

This course is extremely useful in terms of learning Verilog, VHDL, system C. Which also helps later in VLSI design research areas. It also is helpful in understanding synthesis of circuit elements etc.

Prerequisites and Course Contents:

There are no pre-requisites for the course. Course gives introduction to hardware description languages like VHDL, Verilog, System C. The course content put up on ASC was different from what was taught. In class there was detailed discussion on following topics

  • Origin and significance of each language
  • Basic syntax of each language
  • Writing synthesizable (realizable as hardware) code for VHDL and Verilog
  • Differences in these languages in terms of complexity

Feedback on Lectures:

Lectures were good in terms of understanding the basics of HDLs and basics of synthesis in later part of the course. Slides were not very useful though.

Difficulty Level:

The assignments provided in course are quite difficult and time consuming. Each assignment would take almost 3-5 days almost 15 hours of work per week. There will be an assignment each alternate week with deadlines which may exceed by 3-4 days but with penalty. There are 7-8 assignments for the course. Exam is a bit easier but require thorough understanding of HDLs and synthesis. There will be one endsem exam at the end.

Study Material and References:

Prof. VS provide some of the lecture slides(not all). But they won’t help much as they discuss the very basics of HDLs. Most of the times google would help to understand the assignments.

Text/References (According to ASC):

  • R G Gallager and D Bertsekas, Data Networks, Prentice Hall of India, 1992.
  • J F Hayes, Modelling and Analysis of Computer Communication Networks, Plenum Publishing Corporation, New York, 1984.
  • W Stallings, Data and Computer Communications, Prentice Hall of India, 1997.
  • R Rom and M Sidi, Multiple Access Protocols, Springer Verlag, 1990.
  • M DePrycker, ATM-solutions for Broadband ISDN, Prentice Hall of USA, 1995.

Miscellaneous:

The course is extremely knowledgeable. One gets to learn many topics which will later be useful in VLSI design space. The difficulty level is high or very high and course expects lot of dedication. Grading of the course won’t be lenient. You will be expected to get all the results correct in time for all the experiments to get AB/AA. Also you should perform very well in endsem.

Application of Course:

This course would help in all the areas where hardware description is needed, which includes research in testing and verification, VLSI CAD, etc.