Basic Information

  • Course Code: EE 705
  • Course Name: VLSI Design Lab
  • Course Offered In: 2023-2024
  • Semester Season: Spring
  • Instructors: Prof. Sachin Patkar
  • Prerequisites: None. EE671: VLSI Design is a soft prerequisite. I faced no difficulties with this course having not done EE671
  • Difficulty (1 being easy and 5 being tough): 4

Course Content

1) HDL ( VHDL , Verilog ) 2) RTL Simulation (using Modelsim and Iverilog) 3) ASIC Design Flow using OpenLANE 4) FPGA architecture (specifically DE0-Nano based on EP22F17C6 fpga device from Cyclone IV) 5) Validation of RTL design on fpga-kits ( local and remote ) by manual interaction on switches and LEDs and by synthesizing ROM 6) Resource / Area Optimization of RTL code 7) NIOS-II cpu based SoC design, on Cyclone-IV family of fpga devices 8) SoC enhancement by designing and integrating a user designed component with Avalon-Memory-Mapped Slave ( avalon-MM-slave) interface 9) CPU microarchitecture (MIPS) and its fpga implementation 10) Static Timing Analysis ( STA ) in fpga and asic design flows 11) RTL modeling of ( serial ) Communication 12) Use of FIFO 13) Familiarisation with ASIC Tapeout and Test Harness

A project was also given in which we could design any system we want, but it had to interact with a NIOS-II softcore cpu or be compatible with the Caravel SoC Harness for OpenLANE Design Flow.

Feedback on Lectures

There were no lectures as such. We had lab once a week. We were given handouts before each Lab and were encouraged to reach out to the professor and TAs with doubts during Lab hours. The theory covered in handouts required about an hour before each lab to understand, which was very doable. A few times the professor gave extra tasks during the lab which we could complete for extra credit and a deeper understanding of that week’s content. This self-study aspect was very useful for when you missed a lab class as the TAs allowed you to demonstrate work in the next lab.

Feedback on Evaluations

Evaluation Scheme: 1) 35 % weightage for Take-Home Laboratory / Coding tasks 2) 35 % for quizzes ( 15 % ) and mid-sem ( 20 % ) 3) 30 % for course project ( in group of max 4 )

In-lab coding tasks were easy to understand and except a couple of weeks in which we faced bugs in Quartus, they were completed well withing lab hours. The quizzes and midsem were a bit on the difficult side and required you to have a firm grasp on the subject matter taught in the lab handouts. There were no direct questions and the midsem had quite a few questions which combined concepts and forced you to apply intuition rather that rote knowledge. The project took a good chunk of time and almost everyone had to continue working on it post the deadline to have some semblance of a working project. However, the TAs and instructor were very keen on receiving completed projects and thus helped the students accordingly.

The grading scheme was very lenient with 68 AAs and 73 ABs out of 161 students.

Study Material and Resources

The handouts are enough for this course but the following books helped: 1) Rapid Prototyping of Digital Systems - Hamblem et. al. 2) CMOS VLSI Design: A Circuits and Systems Perspective - Weste and Harris

Follow-up Courses

No such courses. You can take EE671 after this course to get a theoretical base in VLSI Design.

Final Takeaway

This is an excellent course for an introduction into the chaotic and yet well-planned world of ASIC Design. It is a must-do course for people interested in a career in Chip Design or just someone who wants to appreciate the effort which goes into building modern digital systems.