EE 709 – TESTING AND VERIFICATION OF VLSI CIRCUITS

Course offered in:

Spring 2013-2014

Instructor:

Prof. Virendra Singh

Motivation:

This course is extremely useful in terms of learning Verilog, VHDL, system C. Which also helps later in VLSI design research areas. It also is helpful in understanding synthesis of circuit elements etc.

Pre-requisities: Circuit Verification Algorithms ~Introduction to VLSI CAD(EE 709)

Course Contents:

*Scope of testing and verification in VLSI design process. *Issues in test and verification of complex chips, embedded cores and SOCs. *Fundamentals of VLSI testing. *Fault models. *Automatic test pattern generation. *Design for testability. *Scan design. *Test interface and and boundary scan. *System testing and test for SOCs. *Delay fault testing. *BIST for testing of logic and memories. *Test automation. *Design verification techniques based on simulation, analytical and formal approaches. *Functional verification. *Timing verification. *Formal verification. *Basics of equivalence checking and model checking. *Hardware emulation.

Feedback on Lectures:

Attendance to the classes is not compulsory and the lecture videos are made available on the CDEEP portal. The classes run at a very slow pace. The lecturer stammers a lot during the classes and is slow in teaching. The content gets boring at times and people tend to bunk classes but it is advised not to because the lecture videos are not interesting either. Moreover, every video is of an hour duration and we are left with many videos to watch in a short span before the exam to follow.

Evaluation Method:

Assignments – 15 Midsem – 15 Endsem – 35 Projects – 20 Bi(tri)weekly surprise tests – 15 Research Project – 15(extra)

Difficulty Level:

It is not a difficult course as far as the content is concerned. However, when it comes to the kind of interest one gets in the course, it tends to get boring at times. Problem solving is necessary for this course and a deep understanding of the concepts is a must.

Grading:

Grading is neither liberal nor tough. The statistics are as follows:

AA 1 AB 9 AP 1 AU 2 BB 17 BC 14 CC 10 CD 7

Study Material and References:

*Essential of Electronic Testing for Digital, Memory, and Mixed Signal VLSI Circuits *Michel. L. Bushnell and Vishwani D. Agrawal *Logic Testing and Design for Testability *Hideo Fujiwara *Digital System Testing and Testable Design *M. Abramovici, M. Breuer, A. Friedman *VLSI Test Principals and Architectures *L.W. Wang, C.W. Wu, and W. Xiaoqing

Feedback on Assignments, Projects and Exams:

Professor hardly uses Moodle and most of the detail is provided during the class. The assignments are generally not based on the topics covered in the week but applications on somewhere from the topics covered in the past and are sometimes very irrelevant to the course content.

There are two projects/big assignments at the end of the semester. These are coding/algorithm based and are time-taking. Project goals are not very informative and change every year and the info-sheet is uploaded with a deadline on the moodle without any email or moodle post.

Exams are very lengthy and are not of a fixed duration. Examinees are allowed to take as much time as they want, even extending upto 5 hours. All form of reading material is allowed ranging from hand-written/printed notes to laptops barring mobile phones. The questions asked in the paper are purely application based and do not focus on literature

Review by:

Harsh Ankur (773895319) (harshankur@outlook.com) with inputs from Vikas Jha (9403453598) (vikasjha.iit@gmail.com) Sundaram Prasad (7506134416) (sundaramp92@gmail.com)

Advanced Courses:

VLSI System Design (EE 668) RF VLSI Design (EE 619) Mixed-Signal VLSI Design (EE 410/719) VLSI Design Lab (EE 705) Digital VLSI Design (EE 671) VLSI Technology (EE 669)