Basic Information
- Course Code: EE 709
- Course Name: Testing and Verification of VLSI Circuits
- Course Offered In: 2023-2024
- Semester Season: Spring
- Instructors: Madhav Desai
- Prerequisites: None
- Difficulty (1 being easy and 5 being tough): 2
Course Content
Scope of testing and verification in VLSI design process. Issues in test and verification of complex chips, embedded cores and SOCs. Fundamentals of VLSI testing. Fault models. Automatic test pattern generation. Design for testability. Scan design. Test interface and and boundary scan. System testing and test for SOCs. Iddq testing. Delay fault testing. BIST for testing of logic and memories. Test automation. Design verification techniques based on simulation, analytical and formal approaches. Functional verification. Timing verification. Formal verification. Basics of equivalence checking and model checking. Hardware emulation.
Feedback on Lectures
The lectures involved the professor covering most of the course content.
Feedback on Evaluations
Quiz: 10 Marks Midsem Take-Home Assignment: 65 marks Homework 2: 5 marks + 5 Bonus Marks Endsem: 50 Marks
The exams were very easy and consisted of a significant portion of the course total. Even a basic understanding of the concepts taught in the lectures and sir’s notes are sufficient to secure good marks in the exams. The assignments were lengthy and coding intensive. They require some basic understanding of the research papers provided by the professor and some basic coding knowledge.
Study Material and Resources
https://drive.google.com/drive/folders/1eZjWSGlnx-RSAlL_KnuOTukBazts2yVf?usp=sharing
Follow-up Courses
VLSI Design, VLSI Design Lab
Final Takeaway
This course is pretty chill overall. It requires understanding of the lecture content and notes provided mostly, and a glance at the research papers to expand your knowledge and get a basic understanding for the assignments.