Secure Booting Sequence on FPGA/Hardware

Basic Information

Project Title / Domain: Secure Booting Sequence on FPGA/Hardware
Name: Natasha Ramineni
Guide: Prof Udayan Ganguly
Project Type: implementation-driven

Short Description of Project

Implementing a secure booting sequence on PULPissimo SoC on FPGAs using TPM architecture that is the standard from TCG.

Whom did you work with?

PG students

Tools / Simulation / Software / Hardware

ModelSim, RISC-V toolchain, PULPissimo SoC, Vivado, ZCU104 FPGA

Expectations from Guide

none as such

Expectations for 8th Sem & Summer

There weren’t much expectations beyond just simple tasks, my project wasn’t confirmed beyond implementing cryptographic algorithms in simulation using RISC-V compiler. I had an “internship” under the prof for the summer so in that I was simulating c-codes for SHA and AES using modelsim for cv32 core

Load: 8th Sem vs 9th (Placement) Sem

there was more load in the 9th semester since I hadn’t done a lot of work before, but i didn’t really do sufficient work in 9th semester either

Summer on Campus

it was just the basics of a RISC-V core in simulation with cryptographic algos, but if i had done that in the placement sem i would have struggled a lot

Is DDP Guide Same as SRE/RnD Guide?

Yes

How did your SRE help with your DDP?

i did a software application of crypto algorithms for the SRE, so that’s why i continued to do crypto algorithms on hardware

End Deliverables

it’s going to be a working base system which can further be implemented in ASIC for the chip that the professor’s start-up is working on

Advice

just be very consistent and communicate with the professor. i had a bit of a communication gap because my mentor is a staff member, so he didn’t really know the pressure of placements timelines and how it could affect my work, and i didn’t talk with my prof about the issues i was facing in implementing stuff in my ddp